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Last updated October, MMXVII by Ulya Karpuzcu.

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  1. ThermoGater: Thermally-Aware On-Chip Voltage Regulation, ISCA 2017.  Acceptance rate: 16.8%.

  2. [Slides] [BibTeX]

  3. AMNESIAC: Trading Computation for Communication for Energy Efficiency, ASPLOS 2017. Acceptance rate: 17.4%.

  4. [Slides] [BibTeX] [Errata]

  5. VARIUS-TC: A Modular Architecture-Level Model of Parametric Variation for Thin-Channel Switches, ICCD 2016. Acceptance rate: 28.9%.

   [Slides] [BibTeX] [Tool Website]

  1. Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks, MICRO 2016. Acceptance rate: 22%.


  1. Comparison of Single-ISA Heterogeneous versus Wide Dynamic Range Processors for Mobile Applications , ICCD 2015. Acceptance rate: 31%.

   [Slides] [BibTeX]

  1. Accordion: Toward Soft Near-threshold Voltage Computing, HPCA 2014. Acceptance rate: 25.6%.

  2. [Slides] [BibTeX]

  3. EnergySmart: Toward Energy-Efficient Many-Cores for Near-Threshold Computing, HPCA 2013. Acceptance rate: 21%.

   [Slides] [BibTeX]

  1. VARIUS-NTV: A Microarchitectural Model to Capture the Increased Sensitivity of Many-Cores to Process Variations at Near-Threshold Voltages, DSN 2012.

  2. Acceptance rate: 17%.  [Slides] [BibTeX] [Tool Website]

  3. LeadOut: Composing Low Overhead Frequency Enhancing Techniques for Single Thread Performance in Configurable Multicores, HPCA 2010.

  4. Acceptance rate: 19%. [Slides] [BibTeX]

  5. The BubbleWrap Many-Core: Popping Cores for Sequential Acceleration, MICRO 2009. Acceptance rate: 24.9%. Best Paper Award.

  6. [Slides] [BibTeX]

  7. Accurate Microarchitecture-level Fault Modeling for Studying Hardware Faults, HPCA 2009. Acceptance rate: 19%.

  8. [BibTeX]

  9. Blueshift: Designing Processors for Timing Speculation from the Ground up, HPCA 2009. Acceptance rate: 19%.

  10. [BibTeX]

Conference Presentations and Posters

  1. BioArch: A Reconfigurable Hardware Accelerator Designed for Bioinformatics Workloads, accepted for presentation in The Cold Spring Harbor Laboratory Conference on Genome Informatics, November 2017. 42 out of approx. 228 submissions (%18.4) accepted as talk.


  1. Binary Neural Networks for Hashing Denovo Transcriptome Sequences, poster in The Southern California Machine Learning Symposium (SoCal ML), October 2017.  [BibTeX]


  1. Efficient In-Memory Processing Using Spintronics, CAL 2017.


  1. Efficiency, Stability, and Reliability Implications of Unbalanced Current Sharing among Distributed On-Chip Voltage Regulators, IEEE TVLSI 2017.


  1. Accuracy Bugs: A New Class of Concurrency Bugs to Exploit Algorithmic Noise Tolerance, ACM TACO 2016.

  2. [HiPEAC Presentation] [BibTeX]

  3. System-Level Power Analysis of a Multicore Multipower Domain Processor with on-chip Voltage Regulators, IEEE TVLSI 2016.


  1. Decoupling Control and Data Processing for Approximate Near-threshold Voltage Computing, IEEE Micro Magazine Special Issue on Heterogeneous Computing, July/August 2015.  [BibTeX]

  2. Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors, IEEE TVLSI, April 2014.

  3. [BibTeX]

  4. Coping With Parametric Variation at Near-Threshold Voltages, IEEE Micro Magazine Special Issue on Reliability, July/August 2013.

  5. [BibTeX]


  1. On Quantification of Accuracy Loss in Approximate Computing, WDDD 2015 (colocated w/ ISCA).

   [Slides] [BibTeX] [Tool Website]

  1. AMNESIAC: Amnesic Automatic Computer, ASPLOS Wild and Crazy Ideas Session 2014.

  2. [Slides]

  3. BubbleWrap: Popping CMP Cores for Per-Thread Performance, ASPLOS Wild and Crazy Ideas Session 2009. Best Idea Award.


  1. Automatic Verilog Code Generation Through Grammatical Evolution, GECCO Undergraduate Student Workshop 2005.

  2. [BibTeX]