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Last updated September, MMXVII by Ulya Karpuzcu.

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  1. Efficient In-Memory Processing Using Spintronics, CAL 2017.


  1. ThermoGater: Thermally-Aware On-Chip Voltage Regulation, ISCA 2017.

  2. [Slides] [BibTeX]

  3. AMNESIAC: Trading Computation for Communication for Energy Efficiency, ASPLOS 2017.

  4. [Slides] [BibTeX]

  5. Efficiency, Stability, and Reliability Implications of Unbalanced Current Sharing among Distributed On-Chip Voltage Regulators, IEEE TVLSI 2017.


  1. Accuracy Bugs: A New Class of Concurrency Bugs to Exploit Algorithmic Noise Tolerance, ACM TACO 2016.

  2. [HiPEAC Presentation] [BibTeX]

  3. VARIUS-TC: A Modular Architecture-Level Model of Parametric Variation for Thin-Channel Switches, ICCD 2016.

   [Slides] [BibTeX] [Tool Website]

  1. Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks, MICRO 2016.


  1. System-Level Power Analysis of a Multicore Multipower Domain Processor with on-chip Voltage Regulators, IEEE TVLSI 2016.


  1. Comparison of Single-ISA Heterogeneous versus Wide Dynamic Range Processors for Mobile Applications , ICCD 2015.

   [Slides] [BibTeX]

  1. On Quantification of Accuracy Loss in Approximate Computing, WDDD 2015 (colocated w/ ISCA).

   [Slides] [BibTeX] [Tool Website]

  1. Decoupling Control and Data Processing for Approximate Near-threshold Voltage Computing, IEEE Micro Magazine Special Issue on Heterogeneous Computing, July/August 2015.  [BibTeX]

  2. AMNESIAC: Amnesic Automatic Computer, ASPLOS Wild and Crazy Ideas Session 2014.

  3. [Slides]

  4. Accordion: Toward Soft Near-threshold Voltage Computing, HPCA 2014.

  5. [Slides] [BibTeX]

  6. Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors, IEEE TVLSI, April 2014.

  7. [BibTeX]

  8. Coping With Parametric Variation at Near-Threshold Voltages, IEEE Micro Magazine Special Issue on Reliability, July/August 2013.

  9. [BibTeX]

  10. EnergySmart: Toward Energy-Efficient Many-Cores for Near-Threshold Computing, HPCA 2013.

   [Slides] [BibTeX]

  1. VARIUS-NTV: A Microarchitectural Model to Capture the Increased Sensitivity of Many-Cores to Process Variations at Near-Threshold Voltages, DSN 2012.

  2. [Slides] [BibTeX] [Tool Website]

  3. LeadOut: Composing Low Overhead Frequency Enhancing Techniques for Single Thread Performance in Configurable Multicores, HPCA 2010.

  4. [Slides] [BibTeX]

  5. The BubbleWrap Many-Core: Popping Cores for Sequential Acceleration, MICRO 2009. Best Paper Award.

  6. [Slides] [BibTeX]

  7. BubbleWrap: Popping CMP Cores for Per-Thread Performance, ASPLOS Wild and Crazy Ideas Session 2009. Best Idea Award.

  8. Accurate Microarchitecture-level Fault Modeling for Studying Hardware Faults, HPCA 2009.

  9. [BibTeX]

  10. Blueshift: Designing Processors for Timing Speculation from the Ground up, HPCA 2009.

  11. [BibTeX]

  12. Automatic Verilog Code Generation Through Grammatical Evolution, GECCO Undergraduate Student Workshop 2005.

  13. [BibTeX]