Conferences 

  1. Mitigation of NBTI Induced Performance Degradation in On-chip Digital LDOs, DATE 2018. Acceptance rate: 23.7%.

    [BibTeX]

  1. ThermoGater: Thermally-Aware On-Chip Voltage Regulation, ISCA 2017.  Acceptance rate: 16.8%.

    [Slides] [BibTeX]

  1. AMNESIAC: Trading Computation for Communication for Energy Efficiency, ASPLOS 2017. Acceptance rate: 17.4%.

    [Slides] [BibTeX] [Errata]

  1. VARIUS-TC: A Modular Architecture-Level Model of Parametric Variation for Thin-Channel Switches, ICCD 2016. Acceptance rate: 28.9%.

    [Slides] [BibTeX] [Tool Website]

  1. Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks, MICRO 2016. Acceptance rate: 22%.

    [BibTeX]

  1. Comparison of Single-ISA Heterogeneous versus Wide Dynamic Range Processors for Mobile Applications , ICCD 2015. Acceptance rate: 31%.

    [Slides] [BibTeX]

  1. Accordion: Toward Soft Near-threshold Voltage Computing, HPCA 2014. Acceptance rate: 25.6%.

    [Slides] [BibTeX]

  1. EnergySmart: Toward Energy-Efficient Many-Cores for Near-Threshold Computing, HPCA 2013. Acceptance rate: 21%.

    [Slides] [BibTeX]

  1. VARIUS-NTV: A Microarchitectural Model to Capture the Increased Sensitivity of Many-Cores to Process Variations at Near-Threshold Voltages,

    DSN 2012. Acceptance rate: 17%. 

    [Slides] [BibTeX] [Tool Website]

  1. LeadOut: Composing Low Overhead Frequency Enhancing Techniques for Single Thread Performance in Configurable Multicores,

    HPCA 2010. Acceptance rate: 19%.

    [Slides] [BibTeX]

  1. The BubbleWrap Many-Core: Popping Cores for Sequential Acceleration, MICRO 2009. Acceptance rate: 24.9%. Best Paper Award.

    [Slides] [BibTeX]

  1. Accurate Microarchitecture-level Fault Modeling for Studying Hardware Faults, HPCA 2009. Acceptance rate: 19%.

    [BibTeX]

  1. Blueshift: Designing Processors for Timing Speculation from the Ground up, HPCA 2009. Acceptance rate: 19%.

    [BibTeX]


Conference Presentations and Posters

  1. BioArch: A Reconfigurable Hardware Accelerator Designed for Bioinformatics Workloads,

    talk in The Cold Spring Harbor Laboratory Conference on Genome Informatics, November 2017.

    [BibTeX]

  1. Binary Neural Networks for Hashing Denovo Transcriptome Sequences,

    poster in The Southern California Machine Learning Symposium (SoCal ML), October 2017. 

    [BibTeX]


Journals

  1. StochMem: Towards Seamless Stochastic Computing Systems with Analog Memories, IEEE CAL 2018.

    [BibTeX]

  1. Approximate Communication: Approximation Techniques for Communication Reduction in Parallel Systems, ACM Computing Surveys 2018.

    [BibTeX]

  1. On Approximate Speculative Lock Elision, IEEE TMSCS 2018.

    [BibTeX]

  1. Efficient In-Memory Processing Using Spintronics, IEEE CAL 2017.

    [BibTeX]

  1. Efficiency, Stability, and Reliability Implications of Unbalanced Current Sharing among Distributed On-Chip Voltage Regulators, IEEE TVLSI 2017.

    [BibTeX]

  1. Accuracy Bugs: A New Class of Concurrency Bugs to Exploit Algorithmic Noise Tolerance, ACM TACO 2016.

    [HiPEAC Presentation] [BibTeX]

  1. System-Level Power Analysis of a Multicore Multipower Domain Processor with on-chip Voltage Regulators, IEEE TVLSI 2016.

    [BibTeX]

  1. Decoupling Control and Data Processing for Approximate Near-threshold Voltage Computing,

    IEEE Micro Magazine Special Issue on Heterogeneous Computing, 2015. 

    [BibTeX]

  1. Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors, IEEE TVLSI, 2014.

    [BibTeX]

  1. Coping With Parametric Variation at Near-Threshold Voltages, IEEE Micro Magazine Special Issue on Reliability, 2013.

    [BibTeX]


Workshops

  1. On Quantification of Accuracy Loss in Approximate Computing, (ISCA) WDDD 2015.

    [Slides] [BibTeX] [Tool Website]

  1. AMNESIAC: Amnesic Automatic Computer, ASPLOS Wild and Crazy Ideas 2014.

    [Slides]

  1. BubbleWrap: Popping CMP Cores for Per-Thread Performance, ASPLOS Wild and Crazy Ideas 2009. Best Idea Award.

    [BibTeX]

  1. Automatic Verilog Code Generation Through Grammatical Evolution, GECCO Undergraduate Student Workshop 2005.

    [BibTeX]

ALTAI Lab.

University of Minnesota, Twin Cities, Department of Electrical and Computer Engineering

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The contents of this page have not been reviewed or approved by the University of Minnesota.

Last updated February, MMXVIII by Ulya Karpuzcu.

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