Conferences 

1. •POWERT Channels: A Novel Class of Covert Communication Exploiting Power Management Vulnerabilities, HPCA 2019. Acceptance rate: 19.7%.
   

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1. •Mitigation of NBTI Induced Performance Degradation in On-chip Digital LDOs, DATE 2018. Acceptance rate: 23.7%.
   

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1. •ThermoGater: Thermally-Aware On-Chip Voltage Regulation, ISCA 2017.  Acceptance rate: 16.8%.
   

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1. •AMNESIAC: Trading Computation for Communication for Energy Efficiency, ASPLOS 2017. Acceptance rate: 17.4%.
   

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1. •VARIUS-TC: A Modular Architecture-Level Model of Parametric Variation for Thin-Channel Switches, ICCD 2016. Acceptance rate: 28.9%.
   

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1. •Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks, MICRO 2016. Acceptance rate: 22%.
   

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1. •Comparison of Single-ISA Heterogeneous versus Wide Dynamic Range Processors for Mobile Applications , ICCD 2015. Acceptance rate: 31%.
   

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1. •Accordion: Toward Soft Near-threshold Voltage Computing, HPCA 2014. Acceptance rate: 25.6%.
   

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1. •EnergySmart: Toward Energy-Efficient Many-Cores for Near-Threshold Computing, HPCA 2013. Acceptance rate: 21%.
   

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1. •VARIUS-NTV: A Microarchitectural Model to Capture the Increased Sensitivity of Many-Cores to Process Variations at Near-Threshold Voltages,
   

    DSN 2012. Acceptance rate: 17%. 

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1. •LeadOut: Composing Low Overhead Frequency Enhancing Techniques for Single Thread Performance in Configurable Multicores,
   

    HPCA 2010. Acceptance rate: 19%.

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1. •The BubbleWrap Many-Core: Popping Cores for Sequential Acceleration, MICRO 2009. Acceptance rate: 24.9%. Best Paper Award.
   

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1. •Accurate Microarchitecture-level Fault Modeling for Studying Hardware Faults, HPCA 2009. Acceptance rate: 19%.
   

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1. •Blueshift: Designing Processors for Timing Speculation from the Ground up, HPCA 2009. Acceptance rate: 19%.
   

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Conference Presentations and Posters

1. •BioArch: A Reconfigurable Hardware Accelerator Designed for Bioinformatics Workloads,
   

    talk in The Cold Spring Harbor Laboratory Conference on Genome Informatics, November 2017.

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1. •De novo Transcriptome Sequencing via Binary Neural Networks,
   

    poster in The Southern California Machine Learning Symposium (SoCal ML), October 2017. 

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Journals

1. •Trading Computation for Communication: A Taxonomy of Data Recomputation Techniques, IEEE TETC 2018.
   

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1. •Exploiting Algorithmic NoiseTolerance for Scalable On-Chip Voltage Regulation, IEEE TVLSI 2018.
   

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1. •A New Class of Covert Channels Exploiting Power Management Vulnerabilities, IEEE CAL 2018.
   

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1. •Toward Dynamic Precision Scaling, IEEE Micro Magazine Special Issue on Approximate Computing, 2018.
   

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1. •In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application Mapping,
   

    IEEE TC Special Issue on Emerging Non-volatile Memory Technologies: from Devices to Architectures and Systems, 2018.

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1. •StochMem: Towards Seamless Stochastic Computing Systems with Analog Memories, IEEE CAL 2018.
   

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1. •Approximate Communication: Approximation Techniques for Communication Reduction in Parallel Systems, ACM Computing Surveys 2018.
   

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1. •On Approximate Speculative Lock Elision, IEEE TMSCS 2018.
   

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1. •Efficient In-Memory Processing Using Spintronics, IEEE CAL 2017.
   

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1. •Efficiency, Stability, and Reliability Implications of Unbalanced Current Sharing among Distributed On-Chip Voltage Regulators, IEEE TVLSI 2017.
   

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1. •Accuracy Bugs: A New Class of Concurrency Bugs to Exploit Algorithmic Noise Tolerance, ACM TACO 2016.
   

    HiPEAC Presentation   BibTeX

1. •System-Level Power Analysis of a Multicore Multipower Domain Processor with on-chip Voltage Regulators, IEEE TVLSI 2016.
   

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1. •Decoupling Control and Data Processing for Approximate Near-threshold Voltage Computing,
   

    IEEE Micro Magazine Special Issue on Heterogeneous Computing, 2015. 

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1. •Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors, IEEE TVLSI, 2014.
   

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1. •Coping With Parametric Variation at Near-Threshold Voltages, IEEE Micro Magazine Special Issue on Reliability, 2013.
   

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Workshops

1. •AISC: Approximate Instruction Set Computer, ASPLOS WAX 2018.
   

    Slides   BibTeX   arXiv

1. •On Quantification of Accuracy Loss in Approximate Computing, ISCA WDDD 2015.
   

    Slides   BibTeX   Tool Website

1. •AMNESIAC: Amnesic Automatic Computer, ASPLOS Wild and Crazy Ideas 2014.
   

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1. •BubbleWrap: Popping CMP Cores for Per-Thread Performance, ASPLOS Wild and Crazy Ideas 2009. Best Idea Award.
   

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1. •Automatic Verilog Code Generation Through Grammatical Evolution, GECCO Undergraduate Student Workshop 2005.
   

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